Renesas H8SX/1520 Series Hardware Manual page 823

32-bit cisc microcomputer

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7.4.3 Activation Sources

(2) Activation by On-Chip Module

7.4.9 DMA Basic Bus Cycle

Figure 7.23 Example of Bus

Timing of DMA Transfer

Section 8 I/O Ports

8.1 Register Descriptions

Figure 8.1 Port Block Diagram

8.1.5 Pull-Up MOS Control

Table 8.3 Input Pull-Up MOS

Section 9 16-Bit Timer Pulse Unit

9.3.5 Timer Status Register (TSR)

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The interrupt request selected as an activation source

can simultaneously generate interrupt requests to the

CPU. For details, see section 5, Interrupt Controller.

When the DMAC is activated with DTA = 1, the

interrupt request flag is automatically cleared by a DMA

When the DMAC is activated with DTA = 0, the

interrupt request flag is not cleared by the DMAC. Thus

it should be cleared by the CPU.

HHWR, HLWR, LHWR

On-chip peripheral module output

On-chip peripheral module output

On-chip peripheral module output

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

Rev. 3.00 Mar. 14, 2006 Page 785 of 804

REJ09B0104-0300

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