Classifi-
cation
Instruction
Arithmetic
MULXU, DIVXU
operations
MULU, DIVU
MULXS, DIVXS
MULS, DIVS
NEG
EXTU, EXTS
TAS
MAC
CLRMAC
LDMAC
STMAC
Logic
AND, OR, XOR
operations
NOT
Shift
SHLL, SHLR
SHAL, SHAR
ROTL, ROTR
ROTXL, ROTXR
Bit
BSET, BCLR,
manipu-
BNOT, BTST,
lation
BSET/cc,
BCLR/cc
BAND, BIAND,
BOR, BIOR,
BXOR, BIXOR,
BLD, BILD, BST,
BIST, BSTZ,
BISTZ
Downloaded from
Elcodis.com
electronic components distributor
Size
#xx
Rn
@ERn
B/W
S:4
SD
W/L
S:4
SD
B/W
S:4
SD
W/L
S:4
SD
B
D
D
W/L
D
D
W/L
D
D
B
D
S
D
B
S
D
B
D
S
B
SD
W/L
S
SD
SD
B
D
D
W/L
D
D
B
D
D
6
B/W/L*
D
D
7
B/W/L*
D
B
D
D
W/L
D
D
B
D
D
B
D
D
Addressing Mode
@(d,
@−ERn/
RnL.B/
@ERn+/
Rn.W/
@ERn−/
@(d,ERn)
ERn.L)
@+ERn
D
D
D
D
D
D
D
D
D
D
D
D
S
S
S
SD
SD
SD
SD
SD
SD
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Rev. 3.00 Mar. 14, 2006 Page 39 of 804
Section 2 CPU
@aa:16/
@aa:8
@aa:32
D
D
D
D
O
D
D
S
S
SD
SD
D
D
D
D
D
D
D
D
D
D
D
D
D
REJ09B0104-0300