Renesas H8SX/1520 Series Hardware Manual page 632

Section 17 Flash Memory (0.18-(m F-ZTAT Version)
(3)
Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU)
FPEFEQ sets the operating frequency of the CPU. The CPU operating frequency available in this
LSI ranges from 8 MHz to 40 MHz.
Bit
Bit Name
Bit
Bit Name
Bit
Bit Name
Bit
Bit Name
Bit Bit Name
31 to 16 
F15 to F0 
15 to 0
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31 30 29
— — —
23 22 21
— — —
15 14 13
F15 F14 F13
7 6 5
F7 F6 F5
Initial
Value R/W
 
R/W
28 27
— —
20 19
— —
12 11
F12 F11
4 3
F4 F3
Description
Unused
These bits should be cleared to 0.
Frequency Set
These bits set the operating frequency of the CPU.
When the PLL multiplication function is used, set the
multiplied frequency. The setting value must be
calculated as follows:
1. The operating frequency shown in MHz units must
be rounded in a number of three decimal places and
be shown in a number of two decimal places.
2. The value multiplied by 100 is converted to the
binary digit and is written to FPEFEQ (general
register ER0).
For example, when the operating frequency of the CPU
is 33.000 MHz, the value is as follows:
1. The number of three decimal places of 33.000 is
rounded.
2. The formula of 33.00 × 100 = 3300 is converted to
the binary digit and B'0000 1100 1110 0100
(H'0CE4) is set to ER0.
26 25 24
— — —
18 17 16
— — —
10 9 8
F10 F9 F8
2 1 0
F2 F1 F0