Renesas H8SX/1520 Series Hardware Manual page 558

Section 14 Synchronous Serial Communication Unit (SSU)
Bit Bit Name
3 TEND
2 TDRE
1 RDRF
Rev. 3.00 Mar. 14, 2006 Page 520 of 804
REJ09B0104-0300
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Initial
Value R/W Description
1 R Transmit End
[Setting condition]
•
•
[Clearing conditions]
•
•
1 R/W Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
0 R/W Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
•
[Clearing conditions]
•
•
When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
When writing 0 after reading TEND = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When writing data to SSTDR
When the TE bit in SSER is 0
When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to.
When writing 0 after reading TDRE = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When writing data to SSTDR with TE = 1
When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
When writing 0 after reading RDRF = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When reading receive data from SSRDR