Renesas H8SX/1520 Series Hardware Manual page 409

Bit Bit Name
7 WOVF
6 RSTE

5

4 to 0
Note: Only 0 can be written to this bit, to clear the flag.
*
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Initial
Value R/W Description
0 R/(W)* Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode, and
only 0 can be written.
[Setting condition]
•
[Clearing condition]
•
0 R/W Reset Enable
Specifies whether or not this LSI is internally reset if
TCNT overflows during watchdog timer operation.
0: LSI is not reset even if TCNT overflows (Though this
1: LSI is reset if TCNT overflows
0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
All 1 R Reserved
These are read-only bits and cannot be modified.
When TCNT overflows (changed from H'FF to H'00)
in watchdog timer mode
Reading RSTCSR when WOVF = 1, and then writing
0 to WOVF
LSI is not reset, TCNT and TCSR in WDT are reset)
Rev. 3.00 Mar. 14, 2006 Page 371 of 804
Section 11 Watchdog Timer (WDT)
REJ09B0104-0300