Renesas H8SX/1520 Series Hardware Manual page 186

Section 7 DMA Controller (DMAC)
Bit Bit Name
11 TSEIE

10
9 ESIE
8 DTIE
Rev. 3.00 Mar. 14, 2006 Page 148 of 804
REJ09B0104-0300
Downloaded from Elcodis.com electronic components distributor
Initial
Value R/W Description
0 R/W Transfer Size Error Interrupt Enable
Enables/disables a transfer size error interrupt.
When the next transfer is requested while this bit is set
to 1 and the contents of the transfer counter is less than
the size of data to be transferred at a single transfer
request, the DTE bit is cleared to 0. At this time, the
ESIF bit is set to 1 to indicate that a transfer size error
interrupt has been requested.
The sources of a transfer size error are as follows:
•
•
0: Disables a transfer size error interrupt request
1: Enables a transfer size error interrupt request
0 R Reserved
This is a read-only bit and cannot be modified.
0 R/W Transfer Escape Interrupt Enable
Enables/disables a transfer escape end interrupt
request. When the ESIF bit is set to 1 with this bit set to
1, a transfer escape end interrupt is requested to the
CPU. The transfer end interrupt request is cleared by
clearing this bit or the ESIF bit to 0.
0: Disables a transfer escape end interrupt
1: Enables a transfer escape end interrupt
0 R/W Data Transfer End Interrupt Enable
Enables/disables a transfer end interrupt request by the
transfer counter. When the DTIF bit is set to 1 with this
bit set to 1, a transfer end interrupt is requested to the
CPU. The transfer end interrupt request is cleared by
clearing this bit or the DTIF bit to 0.
0: Disables a transfer end interrupt
1: Enables a transfer end interrupt
In normal or repeat transfer mode, the total transfer
size set in DTCR is less than the data access size
In block transfer mode, the total transfer size set in
DTCR is less than the block size