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Section 15 A/D Converter
AV
0
CC
AV
SS
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADTRG0
[Legend]
ADCR_0:
ADCSR_0:
ADDRA_0:
ADDRB_0:
ADDRC_0:
Rev. 3.00 Mar. 14, 2006 Page 548 of 804
REJ09B0104-0300
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10-bit D/A
Comparator
Sample-and-
hold circuit
A/D control register_0
A/D control/status register_0
A/D data register A_0
A/D data register B_0
A/D data register C_0
Figure 15.1 Block Diagram of A/D Converter (Unit 0/AD_0)
Module data bus
+
–
Control circuit
ADDRD_0:
A/D data register D_0
ADDRE_0:
A/D data register E_0
ADDRF_0:
A/D data register F_0
ADDRG_0: A/D data register G_0
ADDRH_0:
A/D data register H_0
Internal
data bus
ADI0 interrupt
signal
Conversion start
trigger from the TPU
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