Renesas H8SX/1520 Series Hardware Manual page 429

Bit Bit Name
5 ORER
4 FER
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Initial
Value R/W Description
0 R/(W)* Overrun Error
Indicates that an overrun error has occurred during
reception and the reception ends abnormally.
[Setting condition]
•
[Clearing condition]
•
0 R/(W)* Framing Error
Indicates that a framing error has occurred during
reception in asynchronous mode and the reception ends
abnormally.
[Setting condition]
•
[Clearing condition]
•
Section 12 Serial Communication Interface (SCI)
When the next serial reception is completed while
RDRF = 1
In RDR, receive data prior to an overrun error
occurrence is retained, but data received after the
overrun error occurrence is lost. When the ORER flag
is set to 1, subsequent serial reception cannot be
performed. Note that, in clocked synchronous mode,
serial transmission also cannot continue.
When 0 is written to ORER after reading ORER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the ORER
flag is not affected and retains its previous value.
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is checked
whether it is 1 but the second stop bit is not checked.
Note that receive data when the framing error occurs
is transferred to RDR, however, the RDRF flag is not
set. In addition, when the FER flag is being set to 1,
the subsequent serial reception cannot be performed.
In clocked synchronous mode, serial transmission
also cannot continue.
When 0 is written to FER after reading FER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the FER flag
is not affected and retains its previous value.
Rev. 3.00 Mar. 14, 2006 Page 391 of 804
REJ09B0104-0300