Renesas H8SX/1520 Series Hardware Manual page 129

Bit Bit Name
3 IPSETE
2 CPUP2
1 CPUP1
0 CPUP0
Note: When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits
*
cannot be modified.
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Initial
Value R/W Description
0 R/W Interrupt Priority Set Enable
Controls the function which automatically assigns the
interrupt priority level of the CPU. Setting this bit to 1
automatically sets bits CPUP2 to CPUP0 by the CPU
interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR).
0: Bits CPUP2 to CPUP0 are not updated automatically
1: The interrupt mask bit value is reflected in bits
0 R/(W)* CPU Priority Level 2 to 0
0 R/(W)* These bits set the CPU priority level. When the
CPUPCE is set to 1, the CPU priority control function
0 R/(W)*
over the DMAC becomes valid and the priority of CPU
processing is assigned in accordance with the settings
of bits CPUP2 to CPUP0.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
CPUP2 to CPUP0
Rev. 3.00 Mar. 14, 2006 Page 91 of 804
Section 5 Interrupt Controller
REJ09B0104-0300