Xilinx Virtex-6 Manual page 99

BUFR
Primitive: Regional Clock Buffer for I/O and Logic Resources
Introduction
The regional clock buffer (BUFR) is another available clock buffer. BUFRs drive clock signals to a dedicated clock
net within a clock region, independent from the global clock tree. Each BUFR can drive the six regional clock nets
in the region where it is located, and the six clock nets in the adjacent clock regions (up to three clock regions).
Unlike BUFIOs, BUFRs can drive the I/O logic and logic resources (CLB, block RAM, etc.) in the existing and
adjacent clock regions. BUFRs can be driven by clock-capable pins, local interconnect, GTs, and the MMCMs
high-performance clocks. In addition, BUFR is capable of generating divided clock outputs with respect to the
clock input. The divide values are an integer between one and eight. BUFRs are ideal for source-synchronous
applications requiring clock domain crossing or serial-to-parallel conversion. Each I/O column supports regional
clock buffers. There are up to four I/O columns in a device with two inner columns (center left and right) and up
to two outer left and right columns. The availability of the outer columns are device dependant while the inner
columns are always present. The Virtex®-6 architecture therefore can have up to four BUFRs per region with
two driving from the inner columns out (always present), and two BUFRs per region driving from the outer I/O
columns in (when present). In Virtex-6 devices, BUFRs can also directly drive MMCM clock inputs and BUFGs.
Port Descriptions
Port Direction
CE Input
CLR Input
I Input
O Output
Design Entry Method
Instantiation
Inference
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1 Clock enable port. When asserted low, this port disables the output
clock. When asserted high, the clock is propagated out the O output
port. Cannot be used in "BYPASS" mode. Connect to vcc when
BUFR_DIVIDE is set to "BYPASS" or if not used.
1 Counter asynchronous clear for divided clock output. When asserted
high, this port resets the counter used to produce the divided clock
output and the output is asserted low. Cannot be used in "BYPASS"
mode. Connect to gnd when BUFR_DIVIDE is set to "BYPASS" or
if not used.
1
Clock input port. This port is the clock source port for BUFR. It can
be driven by BUFIO output or local interconnect.
1 Clock output port. This port drives the clock tracks in the clock
region of the BUFR and the two adjacent clock regions. This port
drives FPGA fabric, and IOBs.
Yes
No
Yes
No
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Chapter 4: About Design Elements
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