Xilinx Virtex-6 Manual page 313

RAM64M
Primitive: 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
Introduction
This design element is a 64-bit deep by 4-bit wide, multi-port, random access memory with synchronous write
and asynchronous independent bit wide read capability. This RAM is implemented using the LUT resources of
the device (also known as SelectRAM™) and does not consume any of the block RAM resources of the device.
The RAM64M component is implemented in a single slice, and consists of one 4-bit write, 1-bit read port,
and three separate 1-bit read ports from the same memory allowing for 4-bit write and independent bit read
access RAM. If the DIA, DIB, DIC and DID inputs are all tied to the same data inputs, the RAM can become
a 1 read/write port, 3 independent read port 64x1 quad port memory. If DID is grounded, DOD is not used.
While ADDRA, ADDRB and ADDRC are tied to the same address the RAM becomes a 64x3 simple dual port
RAM. If ADDRD is tied to ADDRA, ADDRB, and ADDRC; then the RAM is a 64x4 single port RAM. There are
several other possible configurations for this RAM.
Port Descriptions
Port
DOA
DOB
DOC
DOD
DIA
DIB
DIC
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction
Output
Output
Output
Output
Input
Input
Input
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Chapter 4: About Design Elements
Width Function
1 Read port data outputs addressed by ADDRA
1 Read port data outputs addressed by ADDRB
1 Read port data outputs addressed by ADDRC
1
Read/Write port data outputs addressed by
ADDRD
1 Write data inputs addressed by ADDRD (read
output is addressed by ADDRA)
1
Write data inputs addressed by ADDRD (read
output is addressed by ADDRB)
1
Write data inputs addressed by ADDRD (read
output is addressed by ADDRC)
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