Xilinx Virtex-6 Manual page 225

LUT5_D
Primitive: 5-Input Lookup Table with General and Local Outputs
Introduction
This design element is a 5-input, 1-output look-up table (LUT) that can either act as an asynchronous 32-bit ROM
(with 5-bit addressing) or implement any 5-input logic function. LUTs are the basic logic building blocks and are
used to implement most logic functions of the design. One LUT5 will be packed into a LUT6 within a slice, or
two LUT5s can be packed into a single LUT6 with some restrictions. The functionality of the LUT5, LUT5_L and
LUT5_D is the same. However, the LUT5_L and LUT5_D allow the additional specification to connect the LUT5
output signal to an internal slice or CLB connection using the LO output. The LUT5_L specifies that the only
connections from the LUT5 will be within a slice or CLB, while the LUT5_D allows the specification to connect
the output of the LUT to both inter-slice/CLB logic and external logic. The LUT5 does not state any specific
output connections and should be used in all cases except where internal slice or CLB signal connections must
be implicitly specified.
An INIT attribute consisting of a 32-bit hexadecimal value must be specified to indicate the LUTs logical function.
The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associated inputs
are applied. For instance, a Verilog INIT value of 32'h80000000 (X"80000000" for VHDL) will make the output
zero unless all of the inputs are one (a 5-input AND gate). A Verilog INIT value of 32'hfffffffe (X"FFFFFFFE" for
VHDL) will make the output one unless all zeros are on the inputs (a 5-input OR gate).
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value is
zero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in most
cases a new INIT value must be determined in order to specify the logic function for the LUT primitive. There
are at least two methods by which the LUT value can be determined:
• The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logic
table. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of
the output and then create the INIT string from those output values.
• The Equation Method -Another method to determine the LUT value is to define parameters for each input
to the LUT that correspond to their listed truth value and use those to build the logic equation. This method
is easier to understand once you have grasped the concept and is more self-documenting than the above
method. However, this method does require the code to first specify the appropriate parameters.
Logic Table
Inputs
I4 I3
0 0
0 0
0 0
0 0
0 0
0 0
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
I2 I1
0 0
0 0
0 1
0 1
1 0
1 0
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Chapter 4: About Design Elements
Outputs
I0 O
0 INIT[0]
1 INIT[1]
0 INIT[2]
1 INIT[3]
0 INIT[4]
1 INIT[5]
LO
INIT[0]
INIT[1]
INIT[2]
INIT[3]
INIT[4]
INIT[5]
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