Xilinx Virtex-6 Manual page 112

Chapter 4: About Design Elements
DSP48E1
Primitive: 25x18 Two's Complement Multiplier with Integrated 48-Bit, 3-Input
Adder/Subtracter/Accumulator or 2-Input Logic Unit
Introduction
This design element is a versatile, scalable, hard IP block within Virtex®-6 that allows for the creation of compact,
high-speed, arithmetic-intensive operations, such as those seen for many DSP algorithms. Some of the functions
capable within the block include multiplication, addition (including pre-adder), subtraction, accumulation,
shifting, logical operations, and pattern detection.
Virtex-6 Libraries Guide for HDL Designs
112 www.xilinx.com UG623 (v 14.5) March 20, 2013