Xilinx Virtex-6 Manual page 273

OBUF
Primitive: Output Buffer
Introduction
This design element is a simple output buffer used to drive output signals to the FPGA device pins that do not
need to be 3-stated (constantly driven). Either an OBUF, OBUFT, OBUFDS, or OBUFTDS must be connected to
every output port in the design.
This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists in
input/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard used
by this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOW
or FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
Port Descriptions
Port Direction
O Output
I Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Data
Attribute Type
DRIVE Integer
IOSTANDARD String
SLEW String
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1 Output of OBUF to be connected directly to top-level output
port.
1
Input of OBUF. Connect to the logic driving the output port.
Allowed Values Default
2, 4, 6, 8, 12, 16, 24 12
See Data Sheet "DEFAULT"
"SLOW" or "FAST" "SLOW"
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Chapter 4: About Design Elements
Yes
Recommended
No
No
Description
Specifies the output current drive strength of
the I/O. It is suggested that you set this to the
lowest setting tolerable for the design drive
and timing requirements.
Assigns an I/O standard to the element.
Specifies the slew rate of the output
driver. Consult the product Data Sheet for
recommendations of the best setting for this
attribute.
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