Xilinx Virtex-6 Manual page 55

MULT_MACRO
Macro: Multiplier
Introduction
The MULT_MACRO simplifies the instantiation of the DSP48 block when used as a simple signed multiplier.
It features parameterizable input and output widths and latencies that ease the integration of the DSP48
block into HDL.
Port Description
Name Direction
Output Ports
P Output
Input Ports
A Input
B Input
CE Input
CLK Input
RST Input
Design Entry Method
This unimacro can be instantiated only. It is a parameterizable version of the primitive.
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width
Variable width, equals the value
of the WIDTH_A attibute plus the
value of the WIDTH_B attribute.
Variable, see WIDTH_A attribute.
Variable, see WIDTH_B attribute.
1
1
1
Yes
No
No
Recommended
www.xilinx.com
Chapter 2: About Unimacros
Function
Primary data output.
Multiplier data input.
Multiplier data input.
Clock Enable.
Clock.
Synchronous Reset.
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