Xilinx Virtex-6 Manual page 251

Attribute
CLOCK_HOLD
COMPENSATION
DIVCLK_DIVIDE
REF_JITTER1
REF_JITTER2
STARTUP_WAIT
CLKFBOUT_USE_
FINE_PS
CLKOUT[0:6]_USE_
FINE_PS
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed
Data Type Values
Boolean FALSE, TRUE
String "ZHOLD",
"BUF_IN",
"CASCADE",
"EXTERNAL",
"INTERNAL"
Integer 1 to 128
3 0.000 to
significant 0.999
digit Float
3 0.000 to
significant 0.999
digit Float
Boolean FALSE
Boolean FALSE, TRUE
Boolean FALSE, TRUE
www.xilinx.com
Chapter 4: About Design Elements
Default Description
FALSE When TRUE, holds the VCO frequency close
to the frequency prior to losing CLKIN.
"ZHOLD" Clock input compensation. Must be set to
ZHOLD. Defines how the MMCM feedback
is configured.
• ZHOLD indicates the MMCM is
configured to provide a negative hold
time at the I/O registers.
• INTERNAL indicates the MMCM is
using its own internal feedback path so
no delay is being compensated.
• EXTERNAL indicates a network
external to the FPGA is being
compensated.
• CASCADE indicates cascading of 2
MMCM.
• BUF_IN indicates that the configuration
does not match with the other
compensation modes and no delay
will be compensated. This is the
case if a clock input is driven by a
BUFG/BUFH/BUFR/GT.
1 Specifies the division ratio for all output
clocks with respect to the input clock.
Effectively divides the CLKIN going into
the PFD.
0.010
Allows specification of the expected jitter
on CLKIN1 in order to better optimize
MMCM performance. A bandwidth setting
of OPTIMIZED will attempt to choose
the best parameter for input clocking
when unknown. If known, then the value
provided should be specified in terms of the
UI percentage (the maximum peak to peak
value) of the expected jitter on the input
clock.
0.010 Allows specification of the expected jitter
on CLKIN2 in order to better optimize
MMCM performance. A bandwidth setting
of OPTIMIZED will attempt to choose
the best parameter for input clocking
when unknown. If known, then the value
provided should be specified in terms of the
UI percentage (the maximum peak to peak
value) of the expected jitter on the input
clock.
FALSE This attribute is not supported.
FALSE CLKFBOUT Counter variable fine phase
shift enable
FALSE CLKOUT[1:6] variable fine phase shift
enable.
251