Xilinx Virtex-6 Manual page 291

PULLDOWN
Primitive: Resistor to GND for Input Pads, Open-Drain, and 3-State Outputs
Introduction
This resistor element is connected to input, output, or bidirectional pads to guarantee a logic Low level for
nodes that might float.
Port Descriptions
Port Direction
O Output
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- PULLDOWN: I/O Buffer Weak Pull-down
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
PULLDOWN_inst : PULLDOWN
port map (
O => O -- Pulldown output (connect directly to top-level port)
);
-- End of PULLDOWN_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1
Pulldown output (connect directly to top level port)
Yes
No
No
No
www.xilinx.com
Chapter 4: About Design Elements
291