Xilinx Virtex-6 Manual page 369

Port
GSR
GTS
KEYCLEARB
PACK
PREQ
TCKSPI
USRCCLKO
USRCCLKTS
USRDONEO
USRDONETS
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
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Chapter 4: About Design Elements
Function
Global Set/Reset (GSR) input (GSR cannot be used for the
port name). This pin is an input from the FPGA fabric. It
drives the state of the Global Set/Reset (GSR) pin manually.
For most applications, this should be tied low.
Global Tristate (GTS) input (GTS cannot be used for the
port name). This pin is an input from the FPGA fabric. It
drives the state of the Global Tristate (GTS) pin manually.
For most applications, this should be tied low.
Clear AES Decrypter Key from Battery-Backed RAM
(BBRAM). This pin is an input from the FPGA fabric. When
held low for 200 ns, it erases the contents of the decryption
keys from the BBRAM. This pin is only enabled if the
PROG_USR attribute is set. It can be tied high for "safe"
operations.
PROGRAM acknowledge input. This pin is an input from
the FPGA fabric. It "acknowledges" the assertion of the
PROG_B signal and allows the remainder of the PROG_B
state machine to continue resetting the FPGA. This pin is
only enabled if PROG_USR attribute is set. It can be tied
low for "safe" operations.
PROGRAM request to fabric output. This pin is an output
into the FPGA fabric. This pin is the "request" from the
PROG_B state machine to reset the device. This allows
the assertion of the PROG_B request to be gated until the
design is in a state where the reset can be completed. This
pin is only enabled if PROG_USR attribute is set. It can be
left open/floating for "safe" operation.
TCK configuration pin access output. This pin is an output
into the FPGA fabric. It is a direct echo of the CCLK clock
being driven onto the FPGA's configuration interface. This
pin is useful for synchronizing an internal state machine
to CCLK.
User CCLK input. This pin is an input from the FPGA
fabric. It drives a custom, fabric-generated clock
frequency onto CCLK at the FPGA pin. This is useful for
post-configuration access of external PROMs (notably SPI
PROMs).
Internal user CCLK 3-state enable. This pin is an input
from the FPGA fabric. It enables the tristate nature of the
FPGA's CCLK pin. Generally, this should be tied low to
prevent tri-stating of the CCLK pin.
Internal user DONE pin output control. This pin is an
input from the FPGA fabric. It directly drives the FPGA
DONE pin.
User DONE 3-state enable. This pin is an input from the
FPGA fabric. It enables the tristate nature of the FPGA's
DONE pin. Generally, this should be tied low. Tying this
high will inhibit the assertion of DONE.
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