Xilinx Virtex-6 Manual page 49

EQ_COMPARE_MACRO
Macro: Equality Comparator
Introduction
The EQ_COMPARE_MACRO simplifies the instantiation of the DSP48 block when used as an equality
comparator. It features parameterizable input and output widths, latencies, mask, and input sources that
ease the integration of the DSP48 block into HDL.
Port Description
Name Direction
Output Ports
Q Output
Input Ports
Input
DATA_IN
DYNAMIC_PATTERN Input
CLK Input
CE Inupt
RST Input
Design Entry Method
This unimacro can be instantiated only. It is a parameterizable version of the primitive.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width
1
Variable width, equals the value
of the WIDTH attribute.
Variable width, equals the value
of the WIDTH attribute.
1
1
1
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Chapter 2: About Unimacros
Function
Active High pattern detection. Detects
match of DATA_IN and the selected
DYNAMIC_PATTERN gated by the MASK.
Result arrives on the same cycle as P.
Input data to be compared
Dynamic data to be compared to DATA_IN
Clock
Clock enable
Synchronous Reset
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