Xilinx Virtex-6 Manual page 370

Chapter 4: About Design Elements
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
If the dedicated global tristate is to be used, connect the appropriate sourcing pin or logic to the GTS input pin of
the primitive. To specify a clock for the startup sequence of configuration, connect a clock from the design to the
CLK pin of this design element. CFGMCLK and CFGCLK allow access to the internal configuration clocks, while
EOS signals the end of the configuration startup sequence.
If you are configuring the device using a SPI PROM, and access to the SPI PROM is necessary after configuration,
use the USRCCLKO and DINSPI pins of the component to gain access to the otherwise dedicated configuration
input pins.
Available Attributes
Attribute
PROG_USR
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- STARTUP_VIRTEX6: STARTUP Block
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
STARTUP_VIRTEX6_inst : STARTUP_VIRTEX6
generic map (
PROG_USR => FALSE -- Activate program event security feature. Requires encrypted bitstreams.
)
port map (
CFGCLK => CFGCLK,
CFGMCLK => CFGMCLK,
DINSPI => DINSPI,
EOS => EOS,
PREQ => PREQ,
TCKSPI => TCKSPI,
CLK => CLK,
GSR => GSR,
GTS => GTS,
KEYCLEARB => KEYCLEARB, -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => PACK,
USRCCLKO => USRCCLKO,
USRCCLKTS => USRCCLKTS, -- 1-bit input: User CCLK 3-state enable input
USRDONEO => USRDONEO,
USRDONETS => USRDONETS
);
-- End of STARTUP_VIRTEX6_inst instantiation
370
Data
Type Allowed Values Default
Boolean FALSE, TRUE
-- 1-bit output: Configuration main clock output
-- 1-bit output: Configuration internal oscillator clock output
-- 1-bit output: DIN SPI PROM access output
-- 1-bit output: Active high output signal indicating the End Of Configuration.
-- 1-bit output: PROGRAM request to fabric output
-- 1-bit output: TCK configuration pin access output
-- 1-bit input: User start-up clock input
-- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
-- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
-- 1-bit input: PROGRAM acknowledge input
-- 1-bit input: User CCLK input
-- 1-bit input: User DONE pin output control
-- 1-bit input: User DONE 3-state enable output
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Recommended
No
No
No
Description
FALSE Activate program event security feature. Can
only be used when an encrypted bitstream is
in use.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013