Xilinx Virtex-6 Manual page 337

Attribute
DOA_REG
DOB_REG
EN_ECC_READ
EN_ECC_WRITE
INIT_A
INIT_B
INIT_FILE
INIT_00 to
INIT_7F
INITP_00 to
INITP_0F
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Data Type Allowed Values
Integer 0, 1
Integer 0, 1
Boolean FALSE, TRUE
Boolean FALSE, TRUE
Hexa-
Any 36 bit value
decimal
Hexa- Any 36 bit value
decimal
String String representing
file name and
location
Hexa- All zeros to all ones
decimal
Hexa-
All zeros to all ones
decimal
www.xilinx.com
Chapter 4: About Design Elements
Default Description
• "GENERATE_X_ONLY" - no
warning, however affected
outputs/memory go unknown (X)
• "NONE"- no warning and affected
outputs/memory retain last value
Note Setting this to a value other than
ALL can allow problems in the design
to go unnoticed during simulation.
Care should be taken when changing
the value of this attribute.
0
A value of 1 enables the output
registers to the RAM enabling quicker
clock-to-out from the RAM at the
expense of an added clock cycle of read
latency. A value of 0 allows a read in
one clock cycle but will result in slower
clock-to-out timing. Applies to port A
in TDP mode and up to 36 lower bits
(including parity bits) in SDP mode.
0
A value of 1 enables the output
registers to the RAM enabling quicker
clock-to-out from the RAM at the
expense of an added clock cycle of read
latency. A value of 0 allows a read in
one clock cycle but will result in slower
clock-to-out timing. Applies to port B
in TDP mode and upper bits (including
parity bits) in SDP mode.
FALSE Enable the ECC decoder circuitry.
FALSE Enable the ECC encoder circuitry.
All zeros Specifies the initial value on the Port
A output after configuration. Applies
to port A in TDP mode and up to 36
lower bits (including parity bits) in
SDP mode.
All zeros Specifies the initial value on the Port
B output after configuration. Applies
to port B in TDP mode and upper bits
(including parity bits) in SDP mode.
NONE File name of file used to specify initial
RAM contents.
All zeros Allows specification of the initial
contents of the 32 kb data memory
array.
All zeros Allows specification of the initial
contents of the 4 kb parity data memory
array.
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