Xilinx Virtex-6 Manual page 43

COUNTER_LOAD_MACRO
Macro: Loadable Counter
Introduction
The COUNTER_LOAD_MACRO simplifies the instantiation of the DSP48 block when used as dynamic loading
up/down counter. It features parameterizable output width and count by values that ease the integration
of the DSP48 block into HDL.
Port Description
Name Direction
Output Ports
Q Output
Input Ports
Input
CE
Input
CLK
Input
LOAD
LOAD_DATA Input
DIRECTION Input
RST Input
Design Entry Method
This unimacro can be instantiated only. It is a parameterizable version of the primitive.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width
Variable, see WIDTH_DATA
attribute.
1
1
Variable, see WIDTH_DATA
attribute.
Variable, see WIDTH_DATA
attribute.
1
1
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Chapter 2: About Unimacros
Function
Counter output.
Clock Enable.
Clock.
When asserted, loads the counter from
LOAD_DATA (two-clock latency).
In a DSP slice, asserting the LOAD pin will force
this data into the P register with a latency of 2
clocks.
High for Up and Low for Down (two-clock
latency)
Synchronous Reset
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