Xilinx Virtex-6 Manual page 26

Chapter 2: About Unimacros
BRAM_TDP_MACRO
Macro: True Dual Port RAM
Introduction
FPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kb
RAM/ROM memories. These block RAM memories offer fast and flexible storage of large amounts of on-chip
data. Both read and write operations are fully synchronous to the supplied clock(s) of the component. However,
READ and WRITE ports can operate fully independently and asynchronous to each other, accessing the same
memory array. Byte-enable write operations are possible, and an optional output register can be used to reduce
the clock-to-out times of the RAM.
Port Description
Name Direction
Output Ports
DOA Output
DOB Output
Input Ports
DIA Input
26
Width
See Configuration Table
below.
See Configuration Table
below.
See Configuration Table
below.
www.xilinx.com
Function
Data output bus addressed by ADDRA.
Data output bus addressed by ADDRB.
Data input bus addressed by ADDRA.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013