Xilinx Virtex-6 Manual page 78

Chapter 4: About Design Elements
Verilog Instantiation Template
// BUFG: Global Clock Buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
BUFG BUFG_inst (
.O(O), // 1-bit output: Clock buffer output
.I(I) // 1-bit input: Clock buffer input
);
// End of BUFG_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
78
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013