Xilinx Virtex-6 Manual page 40

Chapter 2: About Unimacros
ADDSUB_MACRO
Macro: Adder/Subtractor
Introduction
The ADDSUB_MACRO simplifies the instantiation of the DSP48 block when used as a simple adder/subtractor.
It features parameterizable input and output widths and latency that ease the integration of the DSP48 block into
HDL.
Port Description
Name Direction
Output Ports
CARRYOUT Output
RESULT Output
Input Ports
ADDSUB Input
A Input
B Input
CE Input
CARRYIN Input
CLK Input
RST Input
Design Entry Method
This unimacro can be instantiated only. It is a parameterizable version of the primitive.
40
Width (Bits)
1
Variable, see WIDTH attrribute.
1
Variable, see WIDTH attribute.
Variable, see WIDTH attribute.
1
1
1
1
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Function
Carry Out
Data output bus addressed by RDADDR.
When high, RESULT is an addition. When low,
RESULT is a subtraction.
Data input to add/sub.
Data input to add/sub
Clock Enable
Carry In
Clock
Synchronous Reset
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013