Xilinx Virtex-6 Manual page 64

Chapter 2: About Unimacros
Available Attributes
Attribute Data Type
ALMOST_EMPTY_ Hexadecimal
OFFSET
ALMOST_FULL_ Hexadecimal
OFFSET
DATA_WIDTH Integer
DO_REG Binary
FIFO_SIZE String
SIM_MODE String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
-----------------------------------------------------------------
-- DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width --
-- ===========|===========|============|=======================--
-- 37-72 | "36Kb"
-- 19-36 | "36Kb"
-- 19-36 | "18Kb"
-- 10-18 | "36Kb"
-- 10-18 | "18Kb"
-- 5-9 | "36Kb"
-- 5-9 | "18Kb"
-- 1-4 | "36Kb"
-- 1-4 | "18Kb"
-----------------------------------------------------------------
FIFO_SYNC_MACRO_inst : FIFO_SYNC_MACRO
generic map (
DEVICE => "VIRTEX6",
ALMOST_FULL_OFFSET => X"0080",
ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
DATA_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb)
port map (
ALMOSTEMPTY => ALMOSTEMPTY,
ALMOSTFULL => ALMOSTFULL,
64
Allowed
Values Default
Any 13-bit All zeros
Value
Any 13-bit All zeros
Value
1 - 72 4
0,1 1
"18Kb", "18Kb"
"36Kb"
"SAFE", "SAFE"
"FAST"
| 512 | 9-bit
| 1024 | 10-bit
| 512 | 9-bit
| 2048 | 11-bit
| 1024 | 10-bit
| 4096 | 12-bit
| 2048 | 11-bit
| 8192 | 13-bit
| 4096 | 12-bit
-- Target Device: "VIRTEX5, "VIRTEX6"
-- Sets almost full threshold
-- Target BRAM, "18Kb" or "36Kb"
-- 1-bit output almost empty
-- 1-bit output almost full
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Description
Setting determines the difference between EMPTY
and ALMOSTEMPTY conditions. Must be set using
hexadecimal notation.
Setting determines the difference between FULL
and ALMOSTFULL conditions. Must be set using
hexadecimal notation.
Width of DI/DO bus.
DO_REG must be set to 0 for flags and data to
follow a standard synchronous FIFO operation.
When DO_REG is set to 1, effectively a pipeline
register is added to the output of the synchronous
FIFO. Data then has a one clock cycle latency.
However, the clock-to-out timing is improved.
Configures FIFO as 18kb or 36kb memory.
This is a simulation only attribute. It will direct the
simulation model to run in performance-oriented
mode when set to "FAST". Please see the Synthesis
and Simulation Design Guide for more information.
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013