Xilinx Virtex-6 Manual page 186

Chapter 4: About Design Elements
JTAG_SIM_VIRTEX6
Simulation: JTAG TAP Controller Simulation Model
Introduction
This simulation component allows the functional simulation of the JTAG TAP controller interface, functions and
commands to assist with board-level understanding and debug of the JTAG and Boundary-scan behaviors as
well as the behaviors connected to the USER commands and the BSCAN_VIRTEX6 components. This model does
not map to a specific primitive in the FPGA software and cannot be directly instantiated in the design however
can be used in conjunction with the source design if specified either in a simulation-only file like a testbench or
by some means guarded from synthesis so that it is not synthesized into the design netlist. This model may
be used for either functional (RTL) simulation or timing simulation. .
Port Descriptions
Port Direction
TDO Output
TCK Input
TDI Input
TMS Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Xilinx suggests that you instantiate this in a testbench file and not an implementation file or file used during
synthesis of the design. It may be used in conjunction with the design in order to help determine interaction and
start-up sequences between configuration loading and device start-up.
More information on simulating and using this component can be found in the Xilinx Synthesis and Simulation
Design Guide. Please refer to that guide for further detail on using this component.
186
Width Function
1 Test Data Out - This pin is the serial output for all JTAG instruction
and data registers. The state of the TAP controller and the current
instruction determine the register (instruction or data) that feeds
TDO for a specific operation. TDO changes state on the falling edge
of TCK and is only active during the shifting of instructions or data
through the device. TDO is an active driver output.
1 Test Clock - This pin is the JTAG Test Clock. TCK sequences the
TAP controller and the JTAG registers.
1 Test Data - This pin is the serial input to all JTAG instruction and
data registers. The state of the TAP controller and the current
instruction determine the register that is fed by the TDI pin for a
specific operation. TDI has an internal resistive pull-up to provide a
logic High to the system if the pin is not driven. TDI is applied into
the JTAG registers on the rising edge of TCK.
1 Test Mode Select - This pin determines the sequence of states
through the TAP controller on the rising edge of TCK. TMS has
an internal resistive pull-up to provide a logic High if the pin is
not driven.
In testbench or simulation-only file.
No
No
No
www.xilinx.com
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013