Xilinx Virtex-6 Manual page 118

Chapter 4: About Design Elements
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => ACOUT,
BCOUT => BCOUT,
CARRYCASCOUT => CARRYCASCOUT,
MULTSIGNOUT => MULTSIGNOUT,
PCOUT => PCOUT,
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW,
PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => PATTERNDETECT,
UNDERFLOW => UNDERFLOW,
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => CARRYOUT,
P => P,
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN,
BCIN => BCIN,
CARRYCASCIN => CARRYCASCIN,
MULTSIGNIN => MULTSIGNIN,
PCIN => PCIN,
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE,
CARRYINSEL => CARRYINSEL,
CEINMODE => CEINMODE,
CLK => CLK,
INMODE => INMODE,
OPMODE => OPMODE,
RSTINMODE => RSTINMODE,
-- Data: 30-bit (each) input: Data Ports
A => A,
B => B,
C => C,
CARRYIN => CARRYIN,
D => D,
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => CEA1,
CEA2 => CEA2,
CEAD => CEAD,
CEALUMODE => CEALUMODE,
CEB1 => CEB1,
CEB2 => CEB2,
CEC => CEC,
CECARRYIN => CECARRYIN,
CECTRL => CECTRL,
CED => CED,
CEM => CEM,
CEP => CEP,
RSTA => RSTA,
RSTALLCARRYIN => RSTALLCARRYIN,
RSTALUMODE => RSTALUMODE,
RSTB => RSTB,
RSTC => RSTC,
RSTCTRL => RSTCTRL,
RSTD => RSTD,
RSTM => RSTM,
RSTP => RSTP
);
-- End of DSP48E1_inst instantiation
Verilog Instantiation Template
// DSP48E1: 48-bit Multi-Functional Arithmetic Block
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
DSP48E1 #(
// Feature Control Attributes: Data Path Selection
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT"),
.USE_DPORT("FALSE"),
118
-- 30-bit output: A port cascade output
-- 18-bit output: B port cascade output
-- 1-bit output: Cascade carry output
-- 1-bit output: Multiplier sign cascade output
-- 48-bit output: Cascade output
-- 1-bit output: Overflow in add/acc output
-- 1-bit output: Pattern detect output
-- 1-bit output: Underflow in add/acc output
-- 4-bit output: Carry output
-- 48-bit output: Primary data output
-- 30-bit input: A cascade data input
-- 18-bit input: B cascade input
-- 1-bit input: Cascade carry input
-- 1-bit input: Multiplier sign input
-- 48-bit input: P cascade input
-- 4-bit input: ALU control input
-- 3-bit input: Carry select input
-- 1-bit input: Clock enable input for INMODEREG
-- 1-bit input: Clock input
-- 5-bit input: INMODE control input
-- 7-bit input: Operation mode input
-- 1-bit input: Reset input for INMODEREG
-- 30-bit input: A data input
-- 18-bit input: B data input
-- 48-bit input: C data input
-- 1-bit input: Carry input signal
-- 25-bit input: D data input
-- 1-bit input: Clock enable input for 1st stage AREG
-- 1-bit input: Clock enable input for 2nd stage AREG
-- 1-bit input: Clock enable input for ADREG
-- 1-bit input: Clock enable input for ALUMODERE
-- 1-bit input: Clock enable input for 1st stage BREG
-- 1-bit input: Clock enable input for 2nd stage BREG
-- 1-bit input: Clock enable input for CREG
-- 1-bit input: Clock enable input for CARRYINREG
-- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
-- 1-bit input: Clock enable input for DREG
-- 1-bit input: Clock enable input for MREG
-- 1-bit input: Clock enable input for PREG
-- 1-bit input: Reset input for AREG
-- 1-bit input: Reset input for CARRYINREG
-- 1-bit input: Reset input for ALUMODEREG
-- 1-bit input: Reset input for BREG
-- 1-bit input: Reset input for CREG
-- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
-- 1-bit input: Reset input for DREG and ADREG
-- 1-bit input: Reset input for MREG
-- 1-bit input: Reset input for PREG
// Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
// Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
// Select D port usage (TRUE or FALSE)
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013