Xilinx Virtex-6 Manual page 155

IBUFG
Primitive: Dedicated Input Clock Buffer
Introduction
The IBUFG is a dedicated input to the device which should be used to connect incoming clocks to the FPGA's
global clock routing resources. The IBUFG provides dedicated connections from a top level port to the MMCM
or BUFG providing the minimum amount of clock delay and jitter to the device. The IBUFG input can only be
driven by the clock capable (CC) or global clock (GC) pins.
Port Descriptions
Port Direction
O Output
I Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Data
Attribute Type
IOSTANDARD String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFG: Single-ended global clock input buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IBUFG_inst : IBUFG
generic map (
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Clock buffer output
I => I -- Clock buffer input (connect directly to top-level port)
);
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1 Clock Buffer output
1 Clock Buffer input
Allowed Values
See Data Sheet
www.xilinx.com
Chapter 4: About Design Elements
Yes
Recommended
No
No
Default Description
"DEFAULT" Assigns an I/O standard to the
element.
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