Xilinx Virtex-6 Manual page 30

Chapter 2: About Unimacros
Attribute(s) Data Type
SIM_MODE String
SRVAL_A, SRVAL_B Hexa-
decimal
INIT_00 to INIT_FF Hexa-
decimal
INITP_00 to Hexa-
INITP_0F decimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BRAM_TDP_MACRO: True Dual Port RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
--------------------------------------------------------------------------
-- DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width --
-- ===============|===========|===========|===============|=============--
-- 19-36 | "36Kb"
-- 10-18 | "36Kb"
-- 10-18 | "18Kb"
-- 5-9 | "36Kb"
-- 5-9 | "18Kb"
-- 3-4 | "36Kb"
-- 3-4 | "18Kb"
-- 2 | "36Kb"
-- 2 | "18Kb"
-- 1 | "36Kb"
-- 1 | "18Kb"
--------------------------------------------------------------------------
BRAM_TDP_MACRO_inst : BRAM_TDP_MACRO
generic map (
BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
DOA_REG => 0, -- Optional port A output register (0 or 1)
DOB_REG => 0, -- Optional port B output register (0 or 1)
INIT_A => X"000000000", -- Initial values on A output port
INIT_B => X"000000000", -- Initial values on B output port
INIT_FILE => "NONE",
READ_WIDTH_A => 0,
READ_WIDTH_B => 0,
SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
WRITE_WIDTH_A => 0, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
WRITE_WIDTH_B => 0, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
-- The following INIT_xx declarations specify the initial contents of the RAM
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
30
Allowed Values
"SAFE", "FAST" .
Any 72-Bit Value
Any 256-Bit Value
Any 256-Bit Value
| 1024 | 10-bit
| 2048 | 11-bit
| 1024 | 10-bit
| 4096 | 12-bit
| 2048 | 11-bit
| 8192 | 13-bit
| 4096 | 12-bit
| 16384 | 14-bit
| 8192 | 13-bit
| 32768 | 15-bit
| 16384 | 14-bit
-- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
-- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
-- "GENERATE_X_ONLY" or "NONE"
-- Set/Reset value for A port output
-- Set/Reset value for B port output
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Default Description
"SAFE" This is a simulation only attribute. It
will direct the simulation model to run in
performance-oriented mode when set to "FAST."
Please see the Synthesis and Simulation Design
Guide for more information.
All zeroes Specifies the output value of on the DO port
upon the assertion of the synchronous reset (RST)
signal.
All zeroes Allows specification of the initial contents of the
16Kb or 32Kb data memory array.
All zeroes Allows specification of the initial contents of the
2Kb or 4Kb parity data memory array.
| 4-bit --
| 2-bit --
| 2-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
| 1-bit --
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013