Xilinx Virtex-6 Manual page 133

Attribute
FIRST_WORD_FALL_
THROUGH
INIT
SRVAL
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FIFO18E1: 18KB FIFO (First In, First Out) Block RAM Memory
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
FIFO18E1_inst : FIFO18E1
generic map (
ALMOST_EMPTY_OFFSET => X"0080",
ALMOST_FULL_OFFSET => X"0080",
DATA_WIDTH => 4,
DO_REG => 1,
EN_SYN => FALSE,
FIFO_MODE => "FIFO18",
FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to TRUE or FALSE
INIT => X"000000000",
SRVAL => X"000000000"
)
port map (
-- Read Data: 32-bit (each) output: Read output data
DO => DO,
DOP => DOP,
-- Status: 1-bit (each) output: Flags and other FIFO status outputs
ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit output: almost empty output flag
ALMOSTFULL => ALMOSTFULL,
EMPTY => EMPTY,
FULL => FULL,
RDCOUNT => RDCOUNT,
RDERR => RDERR,
WRCOUNT => WRCOUNT,
WRERR => WRERR,
-- Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
RDCLK => RDCLK,
RDEN => RDEN,
REGCE => REGCE,
RST => RST,
RSTREG => RSTREG,
-- Write Control Signals: 1-bit (each) input: Write clock and enable input signals
WRCLK => WRCLK,
WREN => WREN,
-- Write Data: 32-bit (each) input: Write input data
DI => DI,
DIP => DIP
);
-- End of FIFO18E1_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Data Type Allowed Values Default
Boolean FALSE, TRUE
Hexa- Any 36 bit Value
decimal
Hexa-
Any 36 bit Value
decimal
-- Sets the almost empty threshold
-- Sets almost full threshold
-- Sets data width to 4, 9, 18, or 36
-- Enable output register (0 or 1) Must be 1 if EN_SYN = FALSE
-- Specifies FIFO as dual-clock (FALSE) or Synchronous (TRUE)
-- Sets mode to FIFO18 or FIFO18_36
-- Initial values on output port
-- Set/Reset value for output port
-- 32-bit output: data output
-- 4-bit output: parity data output
-- 1-bit output: almost full output flag
-- 1-bit output: empty output flag
-- 1-bit output: full output flag
-- 12-bit output: read count output
-- 1-bit output: read error output
-- 12-bit output: write count output
-- 1-bit output: write error
-- 1-bit input: read clock input
-- 1-bit input: read enable input
-- 1-bit input: clock enable input
-- 1-bit input: reset input
-- 1-bit input: output register set/reset
-- 1-bit input: write clock input
-- 1-bit input: write enable input
-- 32-bit input: data input
-- 4-bit input: parity input
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Chapter 4: About Design Elements
Description
FALSE If TRUE, the first write to the FIFO
appears on DO without a first RDEN
assertion.
All zeros Specifies the initial value on the DO
output after configuration.
All zeros Specifies the output value of the FIFO
upon assertion of the synchronous
reset (RSTREG) signal. Only valid for
DO_REG=1.
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