Xilinx Virtex-6 Manual page 182

Chapter 4: About Design Elements
Available Attributes
Attribute
DATA_RATE
DATA_WIDTH
DYN_CLKDIV_INV_EN
DYN_CLK_INV_EN
INIT_Q1 - INIT_Q4
INTERFACE_TYPE
IOBDELAY
NUM_CE
OFB_USED
182
Data Type Allowed Values
String "DDR", "SDR"
Integer 4, 2, 3, 5, 6, 7, 8, 10
FALSE, TRUE
Boolean
Boolean FALSE, TRUE
Binary 1'b0 to 1'b1
String "MEMORY",
"MEMORY_DDR3",
"MEMORY_QDR",
"NETWORKING"
String "NONE",
"BOTH",
"IBUF",
"IFD"
Integer 2, 1
Boolean FALSE, TRUE
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Default Description
"DDR"
Enables incoming data stream to be
processed as SDR or DDR data.
4 Defines the width of the
serial-to-parallel converter. The legal
value depends on the DATA_RATE
attribute (SDR or DDR).
• If DATA_RATE = DDR, value is
limited to 4, 6, 8, or 10.
• If DATA_RATE = SDR, value is
limited to 2, 3, 4, 5, 6, 7, or 8.
FALSE
Enables DYNCLKDIVINVSEL
inversion when TRUE and disables
HDL inversions on CLKDIV pin.
FALSE Enables DYNCLKINVSEL inversion
when TRUE and disables HDL
inversions on CLK and CLKB pins.
1'b0 Defines the initial value on the Q
outputs.
"MEMORY" Memory or Networking interface type.
"NONE"
Defines input sources for ISERDES
module.
2 Specifies the number of clock enables.
FALSE The OFB port in the ISERDESE1 and
OSERDESE1 can be used to feed the
data transmitted on the OSERDESE1
back to the ISERDESE1. This
feature is enabled when the attribute
OFB_USED = TRUE. The OSERDESE1
and ISERDESE1 must have the same
DATA_RATE and DATA_WIDTH
setting for the feedback to give
the correct data. When using the
ISERDESE1 and OSERDESE1 in width
expansion mode only, connect the
master OSERDESE1 to the master
ISERDESE1. By using the ISERDESE1
as a feedback port, it can not be used
as an input for external data.
Note OFB_USED should be set to
FALSE even if the OFB is used but
only for the delaying of the OSERDES
output
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013