Xilinx Virtex-6 Manual page 300

Chapter 4: About Design Elements
RAM32M
Primitive: 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)
Introduction
This design element is a 32-bit deep by 8-bit wide, multi-port, random access memory with synchronous write
and asynchronous independent, 2-bit, wide-read capability. This RAM is implemented using the LUT resources
of the device known as SelectRAM™, and does not consume any of the Block RAM resources of the device. The
RAM32M is implemented in a single slice and consists of one 8-bit write, 2-bit read port and three separate 2-bit
read ports from the same memory. This configuration allows for byte-wide write and independent 2-bit read
access RAM. If the DIA, DIB, DIC and DID inputs are all tied to the same data inputs, the RAM can become
a 1 read/write port, 3 independent read port, 32x2 quad port memory. If DID is grounded, DOD is not used,
while ADDRA, ADDRB and ADDRC are tied to the same address, the RAM becomes a 32x6 simple dual port
RAM. If ADDRD is tied to ADDRA, ADDRB, and ADDRC, then the RAM is a 32x8 single port RAM. There are
several other possible configurations for this RAM.
Port Descriptions
Port Direction
DOA Output
DOB Output
DOC Output
DOD Output
DIA Input
DIB Input
DIC Input
DID Input
ADDRA Input
300
Width Function
2 Read port data outputs addressed by ADDRA
2 Read port data outputs addressed by ADDRB
2 Read port data outputs addressed by ADDRC
2 Read/Write port data outputs addressed by ADDRD
2 Write data inputs addressed by ADDRD (read output is
addressed by ADDRA)
2
Write data inputs addressed by ADDRD (read output is
addressed by ADDRB)
2
Write data inputs addressed by ADDRD (read output is
addressed by ADDRC)
2 Write data inputs addressed by ADDRD
5 Read address bus A
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013