Xilinx Virtex-6 Manual page 342

Chapter 4: About Design Elements
-- ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
DBITERR => DBITERR,
ECCPARITY => ECCPARITY,
RDADDRECC => RDADDRECC,
SBITERR => SBITERR,
-- Port A Data: 32-bit (each) output: Port A data
DOADO => DOADO,
DOPADOP => DOPADOP,
-- Port B Data: 32-bit (each) output: Port B data
DOBDO => DOBDO,
DOPBDOP => DOPBDOP,
-- Cascade Signals: 1-bit (each) input: BRAM cascade ports (to create 64kx1)
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
-- ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
INJECTDBITERR => INJECTDBITERR, -- 1-bit input: Inject a double bit error
INJECTSBITERR => INJECTSBITERR, -- 1-bit input: Inject a single bit error
-- Port A Address/Control Signals: 16-bit (each) input: Port A address and control signals (read port
-- when RAM_MODE="SDP")
ADDRARDADDR => ADDRARDADDR,
CLKARDCLK => CLKARDCLK,
ENARDEN => ENARDEN,
REGCEAREGCE => REGCEAREGCE,
RSTRAMARSTRAM => RSTRAMARSTRAM, -- 1-bit input: A port set/reset input
RSTREGARSTREG => RSTREGARSTREG, -- 1-bit input: A port register set/reset input
WEA => WEA,
-- Port A Data: 32-bit (each) input: Port A data
DIADI => DIADI,
DIPADIP => DIPADIP,
-- Port B Address/Control Signals: 16-bit (each) input: Port B address and control signals (write port
-- when RAM_MODE="SDP")
ADDRBWRADDR => ADDRBWRADDR,
CLKBWRCLK => CLKBWRCLK,
ENBWREN => ENBWREN,
REGCEB => REGCEB,
RSTRAMB => RSTRAMB,
RSTREGB => RSTREGB,
WEBWE => WEBWE,
-- Port B Data: 32-bit (each) input: Port B data
DIBDI => DIBDI,
DIPBDIP => DIPBDIP
);
-- End of RAMB36E1_inst instantiation
Verilog Instantiation Template
// RAMB36E1: 36K-bit Configurable Synchronous Block RAM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
RAMB36E1 #(
// Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
.SIM_COLLISION_CHECK("ALL"),
// DOA_REG, DOB_REG: Optional output register (0 or 1)
.DOA_REG(0),
.DOB_REG(0),
// Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
// INITP_00 to INITP_0F: Initial contents of the parity memory array
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
342
-- 1-bit output: double bit error status output
-- 8-bit output: generated error correction parity
-- 9-bit output: ECC read address
-- 1-bit output: Single bit error status output
-- 32-bit output: A port data/LSB data output
-- 4-bit output: A port parity/LSB parity output
-- 32-bit output: B port data/MSB data output
-- 4-bit output: B port parity/MSB parity output
-- 1-bit input: A port cascade input
-- 1-bit input: B port cascade input
-- 16-bit input: A port address/Read address input
-- 1-bit input: A port clock/Read clock input
-- 1-bit input: A port enable/Read enable input
-- 1-bit input: A port register enable/Register enable input
-- 4-bit input: A port write enable input
-- 32-bit input: A port data/LSB data input
-- 4-bit input: A port parity/LSB parity input
-- 16-bit input: B port address/Write address input
-- 1-bit input: B port clock/Write clock input
-- 1-bit input: B port enable/Write enable input
-- 1-bit input: B port register enable input
-- 1-bit input: B port set/reset input
-- 1-bit input: B port register set/reset input
-- 8-bit input: B port write enable/Write enable input
-- 32-bit input: B port data/MSB data input
-- 4-bit input: B port parity/MSB parity input
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013