Xilinx Virtex-6 Manual page 16

Chapter 2: About Unimacros
BRAM_SINGLE_MACRO
Macro: Single Port RAM
Introduction
FPGA devices contain several block RAM memories that can be configured as general-purpose 36Kb or 18Kb
RAM/ROM memories. These single-port, block RAM memories offer fast and flexible storage of large amounts
of on-chip data. Byte-enable write operations are possible, and an optional output register can be used to
reduce the clock-to-out times of the RAM.
Port Description
Name Direction
Output Ports
DO Output
Input Ports
DI Input
ADDR Input
WE Input
EN Input
RST Input
REGCE Input
CLK Input
16
Width
See Configuration Table
below.
See Configuration Table
below.
See Configuration Table
below.
See Configuration Table
below.
1
1
1
1
www.xilinx.com
Function
Data output bus addressed by ADDR.
Data input bus addressed by ADDR.
Address input bus.
Byte-Wide Write enable.
Write/Read enables.
Output registers synchronous reset.
Output register clock enable input (valid only when
DO_REG=1)
Clock input.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013