Xilinx Virtex-6 Manual page 125

FDPE
Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset
Introduction
This design element is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset
(PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the
(Q) output High. Data on the (D) input is loaded into the flip-flop when PRE is Low and CE is High on the
Low-to-High clock (C) transition. When CE is Low, the clock transitions are ignored.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-on
conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted
by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic Table
Inputs
PRE CE
1 X
0 0
0 1
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Data
Attribute Type
INIT Binary
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
D
X
X
D
Yes
Recommended
No
No
Allowed
Values Default
0, 1 1
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Chapter 4: About Design Elements
C
X
X
↑
Description
Sets the initial value of Q output after configuration
Outputs
Q
1
No Change
D
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