Xilinx Virtex-6 Manual page 281

ODDR
Primitive: Dedicated Dual Data Rate (DDR) Output Register
Introduction
This design element is a dedicated output register for use in transmitting dual data rate (DDR) signals from
FPGA devices. The ODDR interface with the FPGA fabric is not limited to opposite clock edges. The ODDR
is available with modes that allow data to be presented from the FPGA fabric at the same clock edge. This
feature allows designers to avoid additional timing complexities and CLB usage. In addition, the ODDR works
in conjunction with SelectIO™ features.
ODDR Modes
This element has two modes of operation. These modes are set by the DDR_CLK_EDGE attribute.
• OPPOSITE_EDGE mode - The data transmit interface uses the classic DDR methodology. Given a data and
clock at pin D1-2 and C respectively, D1 is sampled at every positive edge of clock C, and D2 is sampled at
every negative edge of clock C. Q changes every clock edge.
• SAME_EDGE mode - Data is still transmitted at the output of the ODDR by opposite edges of clock C.
However, the two inputs to the ODDR are clocked with a positive clock edge of clock signal C and an extra
register is clocked with a negative clock edge of clock signal C. Using this feature, DDR data can now be
presented into the ODDR at the same clock edge.
Port Descriptions
Port Direction
Q Output
C Input
CE Input
D1 : D2 Input
R Input
Input
S
Design Entry Method
Instantiation
Inference
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Macro support
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1
Data Output (DDR) - The ODDR output that connects to the IOB
pad.
1 Clock Input - The C pin represents the clock input pin.
1 Clock Enable Input - When asserted High, this port enables the
clock input on port C.
1 (each) Data Input - This pin is where the DDR data is presented into
the ODDR module.
1
Reset - Depends on how SRTYPE is set.
1
Set - Active High asynchronous set pin. This pin can also be
Synchronous depending on the SRTYPE attribute.
Recommended
No
No
No
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Chapter 4: About Design Elements
281