Xilinx Virtex-6 Manual page 41

Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
DEVICE
String
LATENCY Integer
WIDTH Integer
WIDTH_RESULT Integer
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ADDSUB_MACRO: Variable width & latency - Adder / Subtractor implemented in a DSP48E
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
ADDSUB_MACRO_inst : ADDSUB_MACRO
generic map (
DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
LATENCY => 2,
WIDTH => 48)
port map (
CARRYOUT => CARRYOUT, -- 1-bit carry-out output signal
RESULT => RESULT,
A => A,
ADD_SUB => ADD_SUB,
B => B,
CARRYIN => CARRYIN,
CE => CE,
CLK =>CLK,
RST => RST
);
-- End of ADDSUB_MACRO_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values
"VIRTEX6",
"SPARTAN6"
0, 1, 2
1-48
1-48
-- Desired clock cycle latency, 0-2
-- Input / Output bus width, 1-48
-- Add/sub result output, width defined by WIDTH generic
-- Input A bus, width defined by WIDTH generic
-- 1-bit add/sub input, high selects add, low selects subtract
-- Input B bus, width defined by WIDTH generic
-- 1-bit carry-in input
-- 1-bit clock enable input
-- 1-bit clock input
-- 1-bit active high synchronous reset
www.xilinx.com
Chapter 2: About Unimacros
Yes
No
No
Recommended
Default Description
"VIRTEX6" Target hardware architecture.
2 Number of pipeline registers.
• 1 - PREG == 1
• 2 - AREG == BREG == CREG ==
PREG
48 A, B, and RESULT port width; internal
customers can override B and RESULT
port widths using other parameters
48 Result port width override.
41