Xilinx Virtex-6 Manual page 51

CLK => CLK, -- 1-bit positive edge clock input
DATA_IN => DATA_IN, -- Input Data Bus, width determined by WIDTH generic
DYNAMIC_PATTERN, => DYNAMIC_PATTERN, -- Input Dynamic Match/Mask Bus, width determined by WIDTH generic
RST => RST -- 1-bit input active high reset
);
-- End of EQ_COMPARE_MACRO_inst instantiation
Verilog Instantiation Template
// EQ_COMPARE_MACRO: Equality Comparator implemented in a DSP48E
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
EQ_COMPARE_MACRO #(
.DEVICE("VIRTEX6"),
.LATENCY(2),
.MASK(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("STATIC_PATTERN"), // "STATIC_PATTERN" = use STATIC_PATTERN parameter,
.STATIC_PATTERN(48'h000000000000), // Specify static pattern, must set SEL_PATTERN = "STATIC_PATTERN"
.WIDTH(48)
) EQ_COMPARE_MACRO_inst (
.Q(Q), // 1-bit output indicating a match
.CE(CE), // 1-bit active high input clock enable
.CLK(CLK), // 1-bit positive edge clock input
.DATA_IN(DATA_IN), // Input Data Bus, width determined by WIDTH parameter
.DYNAMIC_PATTERN(DYNAMIC_PATTERN), // Input Dynamic Match/Mask Bus, width determined by WIDTH parameter
.RST(RST) // 1-bit input active high reset
);
// End of EQ_COMPARE_MACRO_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
// Target Device: "VIRTEX5", "VIRTEX6"
// Desired clock cycle latency, 0-2
// Select bits to be masked, must set SEL_MASK="MASK"
// "MASK" = use MASK parameter,
// "DYNAMIC_PATTERN" = use DYNAMIC_PATTERN input bus
// "DYNAMIC_PATTERN = use DYNAMIC_PATTERN input bus
// Comparator output bus width, 1-48
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Chapter 2: About Unimacros
Sheets).
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