Xilinx Virtex-6 Manual page 267

MUXF8
Primitive: 2-to-1 Look-Up Table Multiplexer with General Output
Introduction
This design element provides a multiplexer function in eight slices for creating a function-of-8 look-up table or a
32-to-1 multiplexer in combination with the associated look-up tables, MUXF5s, MUXF6s, and MUXF7s. Local
outputs (LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The S input is driven from any
internal net. When Low, S selects I0. When High, S selects I1.
Logic Table
Inputs
S I0
0 I0
1 X
X 0
X 1
Port Descriptions
Port Direction
O Output
I0 Input
I1 Input
S Input
Design Entry Method
Instantiation
Inference
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Macro support
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
I1
X
I1
0
1
Width Function
1
Output of MUX to general routing
1 Input (tie to MUXF7 LO out)
1 Input (tie to MUXF7 LO out)
1 Input select to MUX
Yes
Recommended
No
No
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Chapter 4: About Design Elements
Outputs
O
I0
I1
0
1
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