Xilinx Virtex-6 Manual page 92

Chapter 4: About Design Elements
BUFH
Primitive: Clock buffer for a single clocking region
Introduction
The BUFH primitive is provided to allow instantiation capability to access the HCLK clock buffer resources.
The use of this component requires manual placement and special consideration and thus is recommended for
more advanced users. Please refer to the
using this component.
Port Descriptions
Port
I
O
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFH: HROW Clock Buffer for a Single Clocking Region
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
BUFH_inst : BUFH
port map (
O => O, -- 1-bit output: Clock output
I => I -- 1-bit input: Clock input
);
-- End of BUFH_inst instantiation
92
Virtex-6 FPGA Clocking Resources User Guide (UG362)
Direction
Input
Output
www.xilinx.com
Width
1
1
Yes
No
No
No
Virtex-6 Libraries Guide for HDL Designs
for details about
Function
Clock Input
Clock Output
UG623 (v 14.5) March 20, 2013