Xilinx Virtex-6 Manual page 106

Chapter 4: About Design Elements
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
• Connect the CLK input to the clock source used to supply the reconfiguration data.
• Connect the CDI input to the source of the reconfiguration data.
• Connect the CE pin to the active high logic if you need to enable/disable LUT reconfiguration.
• Connect the I4-I0 pins to the source inputs to the logic equation. The logic function is output on O6 and O5.
• To cascade this element, connect the CDO pin from each element to the CDI input of the next element to
allow a single serial chain of data to reconfigure multiple LUTs.
The INIT attribute should be placed on this design element to specify the initial logical function of the LUT. A
new INIT can be loaded into the LUT any time during circuit operation by shifting in 32-bits per LUT in the
chain, representing the new INIT value. Disregard the O6 and O5 output data until all 32-bits of new INIT data
has been clocked into the LUT. The logical function of the LUT changes as new INIT data is shifted into it. Data
should be shifted in MSB (INIT[31]) first and LSB (INIT[0]) last.
In order to understand the O6 and O5 logical value based on the current INIT, see the table below:
I4 I3 I2 I1 I0
1 1 1 1 1
1 1 1 1 0
. . .
1 0 0 0 1
1 0 0 0 0
0 1 1 1 1
0 1 1 1 0
. . .
0 0 0 0 1
0 0 0 0 0
For instance, the INIT value of FFFF8000 would represent the following logical equations:
• O6 = I4 or (I3 and I2 and I1 and I0)
• O5 = I3 and I2 and I1 and I0
To use these elements as two, 4-input LUTs with the same inputs but different functions, tie the I4 signal to a
logical one. The INIT[31:16] values apply to the logical values of the O6 output and INIT [15:0] apply to the
logical values of the O5 output.
Available Attributes
Attribute Data Type
INIT
Hexadecimal
106
Recommended
No
No
No
O6 Value
INIT[31]
INIT[30]
. . .
INIT[17]
INIT[16]
INIT[15]
INIT[14]
. . .
INIT[1]
INIT[0]
Allowed Values
Any 32-bit Value
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O5 Value
INIT[15]
INIT[14]
. . .
INIT[1]
INIT[0]
INIT[15]
INIT[14]
. . .
INIT[1]
INIT[0]
Default Description
All zeros Specifies the initial logical expression of
this element.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013