Xilinx Virtex-6 Manual page 52

Chapter 2: About Unimacros
MACC_MACRO
Macro: Multiplier/Accumulator
Introduction
The MACC_MACRO simplifies the instantiation of the DSP48 block when used in simple signed
multiplier/accumulator mode. It features parameterizable input and output widths and latencies that ease the
integration of the DSP48 block into HDL.
Port Description
Name Direction
Output Ports
P Output
Input Ports
A Input
B Input
CARRYIN Input
Input
CE
Input
CLK
Inupt
LOAD
Input
LOAD_DATA
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Width
Variable width, equals the value
of the WIDTH_A attibute plus the
value of the WIDTH_B attribute.
Variable, see WIDTH_A attribute.
Variable, see WIDTH_B attribute.
1
1
1
1
Variable width, equals the value
of the WIDTH_A attibute plus the
value of the WIDTH_B attribute.
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Function
Primary data output.
Multiplier data input.
Multiplier data input.
Carry input.
Clock enable.
Clock.
Load.
In a DSP slice, when LOAD is asserted, loads P
with A*B+LOAD_DATA.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013