Xilinx Virtex-6 Manual page 341

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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
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-- INIT_A, INIT_B: Initial values on output ports
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
-- RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
-- READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
READ_WIDTH_A => 0,
READ_WIDTH_B => 0,
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 0,
-- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
-- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Cascade Signals: 1-bit (each) output: BRAM cascade ports (to create 64kx1)
CASCADEOUTA => CASCADEOUTA,
CASCADEOUTB => CASCADEOUTB,
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
-- 1-bit output: A port cascade output
-- 1-bit output: B port cascade output
www.xilinx.com
Chapter 4: About Design Elements
-- RAM initialization
-- file
-- "SDP" or "TDP"
-- "PERFORMANCE" or
-- "DELAYED_WRITE"
-- 0, 1, 2, 4, 9, 18,
-- 36, or 72
-- 0, 1, 2, 4, 9, 18, or
-- 36
-- 0, 1, 2, 4, 9, 18, or
-- 36
-- 0, 1, 2, 4, 9, 18,
-- 36, or 72
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