Xilinx Virtex-6 Manual page 320

Chapter 4: About Design Elements
RAM64X1S
Primitive: 64-Deep by 1-Wide Static Synchronous RAM
Introduction
This design element is a 64-word by 1-bit static random access memory (RAM) with synchronous write capability.
When the write enable is set Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM
is not affected. When WE is set High, any positive transition on WCLK loads the data on the data input (D)
into the word selected by the 6-bit address (A5:A0). This RAM block assumes an active-High WCLK. However,
WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by
the values on the address pins.
You can initialize this element during configuration using the INIT attribute.
Logic Table
Mode selection is shown in the following logic table
Inputs
WE (mode)
0 (read)
1 (read)
1 (read)
1 (write)
1 (read)
Data = word addressed by bits A5:A0
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
320
WCLK D
X X
0 X
1 X
↑
D
↓
X
www.xilinx.com
Yes
Recommended
No
No
Virtex-6 Libraries Guide for HDL Designs
Outputs
O
Data
Data
Data
D
Data
UG623 (v 14.5) March 20, 2013