Xilinx Virtex-6 Manual page 284

Chapter 4: About Design Elements
Port Descriptions
Port
CLK
CLKDIV
CLKPERF
CLKPERFDELAY
D1 - D6
OCBEXTEND
OCE
ODV
OFB
OQ
284
Direction Width Function
Input 1
High Speed Clock Input - This clock input is used to drive the
parallel-to-serial converters.
Input 1 This divided high-speed clock input drives the parallel side of the
parallel-to-serial converters. This clock is the divided version of
the clock connected to the CLK port.
Input 1 This port is part of a dedicated path that provides a
high-performance clock from the MMCM to the OSERDESE1.
CLKPERF is only available in MEMORY_DDR3 mode for DDR3
applications.
Input 1 This port (CLKPERFDELAY) is part of a dedicated path that
provides a high-performance clock from the MMCM delayed
with the IODELAYE1 to OSERDESE1. CLKPERFDELAY is only
available in MEMORY_DDR3 mode for DDR3 applications. When
the IODELAYE1 is not being used to delay the CLKPERF, connect
CLKPERFDELAY to the same source as CLKPERF.
Input 1 Parallel Data Inputs - All incoming parallel data enters the
OSERDES module through ports D1 to D6. These ports are
connected to the FPGA fabric, and can be configured from two to
six bits (i.e., a 6:1 serialization). Bit widths greater than six (up to
10) can be supported by using a second OSERDES in SLAVE mode.
Output 1 Used in DDR3 mode to signal that the output circular buffer
has extended the latency to match the CLK to the CLKPERF or
CLKPERFDELAY.
Input 1 OCE is an active High clock enable for the data path.
Input 1 The ODV port is a part of the dedicated logic for the
MEMORY_DDR3 mode. The ODV is asserted High by the user
when CLKPERFDELAY delay through the IODELAYE1 is greater
than half of the period. ODV is only available in MEMORY_DDR3
mode for DDR3 applications. When not using MEMORY_DDR3
mode, connect this port to GND.
Output 1 The output feedback port (OFB) is the serial (high-speed) data
output port of the OSERDESE1 or the bypassed version of the
CLKPERF. When the attribute ODELAYUSED is set to 0, the OFB
port can be used to send out serial data to the ISERDESE1. When
the attribute ODELAYUSED is set to 1 and the OSERDESE1 is in
MEMORY_DDR3 mode, the OFB port can be used to link the
high-performance clock input (CLKPERF) to the IODELAYE1.
Output 1 The OQ port is the data output port of the OSERDES module. Data
at the input port D1 will appear first at OQ. This port connects the
output of the data parallel-to-serial converter to the data input
of the IOB. This port can not drive the IODELAYE1; the OFB pin
must be used.
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013