Xilinx Virtex-6 Manual page 253

CLKOUT5 => CLKOUT5,
CLKOUT6 => CLKOUT6,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => DO,
DRDY => DRDY,
-- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
PSDONE => PSDONE,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
CLKFBOUTB => CLKFBOUTB,
-- Status Ports: 1-bit (each) output: MMCM status ports
CLKFBSTOPPED => CLKFBSTOPPED, -- 1-bit output: Feedback clock stopped output
CLKINSTOPPED => CLKINSTOPPED, -- 1-bit output: Input clock stopped output
LOCKED => LOCKED,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => CLKIN1,
CLKIN2 => CLKIN2,
-- Control Ports: 1-bit (each) input: MMCM control ports
CLKINSEL => CLKINSEL,
PWRDWN => PWRDWN,
RST => RST,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => DADDR,
DCLK => DCLK,
DEN => DEN,
DI => DI,
DWE => DWE,
-- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
PSCLK => PSCLK,
PSEN => PSEN,
PSINCDEC => PSINCDEC,
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
-- End of MMCM_ADV_inst instantiation
Verilog Instantiation Template
// MMCM_ADV: Advanced Mixed Mode Clock Manager
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
MMCM_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(5.0),
.CLKFBOUT_PHASE(0.0),
// CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKIN1_PERIOD(0.0),
.CLKIN2_PERIOD(0.0),
.CLKOUT0_DIVIDE_F(1.0),
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
// CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
-- 1-bit output: CLKOUT5 output
-- 1-bit output: CLKOUT6 output
-- 16-bit output: DRP data output
-- 1-bit output: DRP ready output
-- 1-bit output: Phase shift done output
-- 1-bit output: Feedback clock output
-- 1-bit output: Inverted CLKFBOUT
-- 1-bit output: LOCK output
-- 1-bit input: Primary clock input
-- 1-bit input: Secondary clock input
-- 1-bit input: Clock select input
-- 1-bit input: Power-down input
-- 1-bit input: Reset input
-- 7-bit input: DRP adrress input
-- 1-bit input: DRP clock input
-- 1-bit input: DRP enable input
-- 16-bit input: DRP data input
-- 1-bit input: DRP write enable input
-- 1-bit input: Phase shift clock input
-- 1-bit input: Phase shift enable input
-- 1-bit input: Phase shift increment/decrement input
-- 1-bit input: Feedback clock input
// Jitter programming ("HIGH","LOW","OPTIMIZED")
// Multiply value for all CLKOUT (5.0-64.0).
// Phase offset in degrees of CLKFB (0.00-360.00).
// Divide amount for CLKOUT0 (1.000-128.000).
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Chapter 4: About Design Elements
253