Xilinx Virtex-6 Manual page 36

Chapter 2: About Unimacros
.DOB(DOB), // Output port-B data, width defined by READ_WIDTH_B parameter
.ADDRA(ADDRA), // Input port-A address, width defined by Port A depth
.ADDRB(ADDRB), // Input port-B address, width defined by Port B depth
.CLKA(CLKA), // 1-bit input port-A clock
.CLKB(CLKB), // 1-bit input port-B clock
.DIA(DIA), // Input port-A data, width defined by WRITE_WIDTH_A parameter
.DIB(DIB), // Input port-B data, width defined by WRITE_WIDTH_B parameter
.ENA(ENA), // 1-bit input port-A enable
.ENB(ENB), // 1-bit input port-B enable
.REGCEA(REGCEA), // 1-bit input port-A output register enable
.REGCEB(REGCEB), // 1-bit input port-B output register enable
.RSTA(RSTA), // 1-bit input port-A reset
.RSTB(RSTB), // 1-bit input port-B reset
.WEA(WEA), // Input port-A write enable, width defined by Port A depth
.WEB(WEB) // Input port-B write enable, width defined by Port B depth
);
// End of BRAM_TDP_MACRO_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
36
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013