Xilinx Virtex-6 Manual page 361

Verilog Instantiation Template
// SIM_CONFIG_V6_SERIAL: Behavioral Simulation-only Model of FPGA Serial Configuration
//
// Xilinx HDL Libraries Guide, version 14.5
SIM_CONFIG_V6_SERIAL #(
.DEVICE_ID(32'h00000000)
) SIM_CONFIG_V6_SERIAL_inst (
.DONE(DONE), // 1-bit bi-directional Done pin
.DOUT(DOUT), // 1-bit data output pin
.CCLK(CCLK), // 1-bit input configuration clock
.DIN(DIN), // 1-bit input configuration data
.INITB(INITB), // 1-bit bi-directional INIT status pin
.M(M), // 3-bit input Mode pins
.PROGB(PROGB) // 1-bit input Program pin
);
// End of SIM_CONFIG_V6_SERIAL_inst instantiation
For More Information
• See the Synthesis and Simulation Design Guide
• See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Virtex-6
// Specify DEVICE_ID
(UG626).
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