Xilinx Virtex-6 Manual page 156

Chapter 4: About Design Elements
-- End of IBUFG_inst instantiation
Verilog Instantiation Template
// IBUFG: Single-ended global clock input buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
IBUFG #(
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT")
) IBUFG_inst (
.O(O), // Clock buffer output
.I(I) // Clock buffer input (connect directly to top-level port)
);
// End of IBUFG_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
156
// Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
// Specify the input I/O standard
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013